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XE1205
7.1.1
Chip configuration via SPI_CONFIG interface
The SPI_CONFIG interface is selected if NSS_CONFIG is low even if the circuit is in buffered mode and NSS_DATA is
low (SPI_CONFIG has priority). To configure the transceiver two bytes are required; the first byte contains a start bit
(equal to 0), R/W information (‘1’ for a read operation or ‘0’ for a write operation), 5 bits for the address of the register
and finally a stop bit (equal to ‘1’). The second byte contains the data to be sent in write mode or the new address to
read from in read mode. Figure 15 shows the timing diagram for a typical write sequence:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
New value of
register A1*
MOSI
start
rw
A(4) A(3) A(2) A(1) A(0) stop D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Data at address
Address = A1
A1*
MISO
HZ
x
x
x
x
x
x
x
x
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
D(0)
HZ
NSS_CONFIG
* when writing the new data at address A1,
the previous contents of A1 can be read by the micro-controller
Figure 15: Write sequence when sending a new configuration to the XE1205 via the SPI _CONFIG
NSS_CONFIG must remain low during the transmission of the two bytes (address and data); if it goes high after the first
byte, then the next byte will be considered as an address byte. When writing more than one register successively,
NSS_CONFIG does not need to make a high to low transmission between two write sequences. The bytes are
alternatively considered as an address byte followed by a data byte.
The read sequence via the SPI_CONFIG interface is similar to the write one except that the data byte contains all zeroes
? Semtech 2008
25
www.semtech.com
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